Patent application Ser. No. 912,457 describes a plural-chip integrated circuit in which a number of monolithic integrated-circuit chips are flush-mounted in wells located on the surface of a common substrate and covered over with an insulating polyimide layer. These chips are connected to each other and to on-substrate metallization by High Density Interconnection (HDI) technology. The HDI connections are made through vias in the polyimide layer to bond pads as small as 25 microns across, which can be placed anywhere on the surfaces of the monolithic i-c chips or on the substrate; and connections can be made routing right over active portions of the integrated circuits by virtue of the intervening insulating polyimide layer. Up to four layers of metal interconnection separated by insulating polyimide layers may be used. A limited number of conventional-size bond pads allowing for plural-chip i-c pin-out are provided on the substrate.
Also described is the testing circuitry included within each monolithic i-c chip. Each chip includes a serial-in/parallel-out (SIPO) register for receiving a succession of test vectors supplied thereto in bit-serial form and for cyclically applying that succession of test vectors in bit-parallel form, either to the input ports of the chip or to each output port of each preceding chip as selected by test mode signals. Each chip includes a parallel-in/serial-out (PISO) register for receiving test results in parallel-bit form, either from the output ports of the chip or from each input port of each succeeding chip as selected by test mode signals, and converting the test results to bit-serial output form. The SIPO registers on the chips are also provided with serial-out capabilities, permitting their cascade interconnection as an extended shift register, through which test vectors supplied in serial form may be successively written to each of the SIPO registers. Similarly, the PISO registers on the chips are also provided with serial-in capabilities, permitting their cascade interconnection as another extended shift register, through which test results may be successively read in serial form from each of the PISO registers.
Patent application Ser. Nos. 487,481 and 513,636 each describe a more recently developed and preferred type of monolithic integrated circuit chip with built-in test capability, in which the component SIPO and PISO registers included in each chip can be accessed on an individual, rather than a serial, basis.
Occasions arise, particularly where the fast system prototyping capability of HDI technology is being taken advantage of, in which a system is designed to include off-the-shelf i-c chips. Since customarily i-c chips specifically for use in HDI technology are designed with output drive capability only sufficient to drive the low-capacitance high-density interconnections, and since off-the-shelf i-c chips have large bond pads that exhibit larger capacitances, where speeds of response are to be maintained in transferring data from an i-c chip specifically designed for HDI use to an off-the-shelf i-c chip, a high-speed buffer will be needed to interface between those i-c chips. This high-speed buffer will include a buffer amplifier with substantial output drive capability for each bit line in the interface and will be constructed on a separate i-c chip.
It is useful to include built-in test capability for the buffer that is compatible with that for the i-c chips designed specifically for HDI use. This built-in test circuitry should provide for the testing of interconnections to the buffer chip from a preceding i-c chip designed specifically for HDI use, which provision can be readily implemented because the designs of both i-c chips can take into consideration the constraints of HDI technology. Provision must be made for applying test input signals from the input port of the buffer chip to the output port of a preceding chip specifically designed for HDI use.
Provision for the testing of interconnections from the buffer i-c chip to a succeeding off-the-shelf i-c chip is complicated by the fact that the off-the-shelf i-c chip customarily has no provision for built-in testing that allows the driving of test input signals from it back to the preceding buffer i-c chip. (The testing of interconnections between two i-c chips designed for HDI use is usually implemented, as previously noted, by driving test input signals back from the succeeding i-c chip to the preceding i-c chip.) The testing of interconnections from the buffer i-c chip to the succeeding off-the-shelf chip must therefore be done as part of testing the functionality of the off-the-shelf i-c chip by driving test input signals from the preceding buffer i-c chip to the input port(s) of the off-the-shelf i-c chip and by sensing test response signals from the output port(s) of the off-the-shelf i-c chip. (During testing, if the off-the-shelf i-c chip has a plurality of signal-input ports during normal or non-test operating conditions, they are considered portions of a single test-input port having a bit-width equal to the sum of the bit-widths of the individual signal-input ports; and, if the off-the-shelf i-c chip has a plurality of signal-output ports during normal or non-test operating conditions, similarly, they are considered portions of a single test-output port.) If the off-the-shelf i-c chip connected directly to an i-c chip designed for HDI use, there would be no means available for sensing the test response at the test-output port of the off-the-shelf i-c chip. This is because an i-c chip designed for HDI use is not designed to sense the conditions at its input port(s) during testing, but rather is designed only to sense conditions at its output port(s) during testing. It becomes necessary then to insert a testing interface for sensing test responses after the off-the-shelf i-c chip, which testing interface is provided by another i-c chip.
Where there are two off-the-shelf i-c chips in cascade, it is preferable to test the interconnections to the earlier chip, by testing just the functionality of that earlier chip, rather than by testing the combined functionality of both off-the-shelf i-c chips. Accordingly, there should be inserted between the two off-the-shelf i-c chips an i-c chip providing the capability of sensing test responses. It is also preferable to test the interconnections from the later off-the-shelf chip to the succeeding chip designed for HDI use by testing just the functionality of that later chip, rather than the combined functionality of both off-the-shelf chips. Accordingly, there should be inserted between the two off-the-shelf chips a chip providing for driving input test signals into the latter of them.
A single i-c buffer chip with capabilities of providing buffer amplification, sensing test responses, and driving test signals back through its input port reduces the variety of chips required to interface between off-the-shelf i-c chips and i-c chips specifically designed for HDI use. A respective buffer chip with such combined capabilities can be used before each off-the-shelf i-c chip and can also be used after each off-the-shelf i-c chip not otherwise followed by another chip. Also, a respective buffer chip with such combined capabilities can be used after each chip with built-in testing capability not otherwise followed by another chip, in order to provide low-impedance drive capabilities together with the means to test the interconnections to that buffer chip.
To facilitate testing the interconnections to a succeeding chip specifically designed for HDI use, the single i-c chip combining buffer amplification and built-in testing capability will include means for disabling its buffer amplification function during such testing. The low source impedances associated with buffer amplification are not applied to the interconnections currently under test, in order to avoid short-circuiting responses to the interconnection test. This can be implemented using tristate drivers as the buffer amplifiers for each bit-place in the output port of the buffer.